High-speed hardware implementation of fixed and runtime variable window length 1-D median filters

Supplementary Results

Nonlinear digital filters play an important role in digital signal processing applications. In this paper, a novel architecture is proposed for the hardware implementation of fixed and run-time variable window length one-dimensional (1-D) median filters. In the proposed architecture, the maximum working clock frequency is almost independent of the median filter window length, while the hardware complexity is proportional to the number of samples in the window. This feature enables the construction of filters with relatively large window lengths with negligible reduction in the maximum clock frequency; while in previous architectures the maximum clock frequency drops significantly as the window length is increased. The benchmark results show the efficiency of the proposed architecture in comparison with state-of-the-art techniques.

The following additional analyses have been carried-out during the revision and are brought here for reviewers' information. However, due to the lack of space only a summary of these results has been added to the paper.
1- Detailed post-synthesis power results for the variable length case
The detailed dynamic and static power consumption ratios are as follows. The power result are extracted from Design Compiler Tool by setting true the "power_preserve_rtl_hier_names" attribute. In Table IV of the paper, only the total power (static plus dynamic) have been added to save space.

MAXIMUM THROUGHPUT, AREA AND POWER RESULTS FOR VARIABLE WINDOW LENGTH ON 45NM CMOS ASIC

2- FPGA-based implementation
For FPGA implementation, the Quartus II 12.1 from Altera was used as the synthesis tool and an Altera Cyclone IVE FPGA with the following specifications was used as the target device: chip number EP4CE115F29I8L, 114480 logic cells, 3981312 memory bits, 1.0v core voltage. Tables I to V show the results for fixed window length in terms of maximum clock frequency and logic cells with 8-bit and 16-bit word lengths, respectively. As expected the overall trend of the maximum frequencies and area are the same as the ASIC results. Table III repeat these results for variable length filter.

Table I. Maximum Frequency And Area Results For Fixed Window Length And 8-Bit Word Length On Altera Cyclone IVE FPGA

Table II. Maximum Frequency And Area Results For Fixed Window Length And 16-Bit Word Length On Altera Cyclone IVE FPGA

Table III. Maximum Frequency And Area FPGA Results For Variable Window Size, 8-Bit And 16-Bit Word Length

Table IV. Hardware Utilization For Fixed Window Length And 8-bit Word Length On FPGA

Table V. Hardware Utilization For Fixed Window Length And 16-bit Word Length On FPGA

3- Detailed hardware utilization
In Comparison with the latest work, Chen[10], our ASIC results show that in the proposed architecture for different sizes, the combinational area occupies about 42%-44% of the total area, non-combinational area takes up 32% and the net interconnections area occupies about 24% -26% of the total area. These results for the Chen [10] are 47%-49%, 24%-26% and 25%-27% respectively. These results are reflected in Tables IV, and V. Considering only the component areas (as noted by one of the reviewers), we have: For different word and window lengths, the average resource utilization ratio of the proposed architecture is as follows: the combinational area occupies about 57% and the noncombinational area takes 43% (27% of which is due to the register chain), of the total component areas. For Chen's architecture, these ratios are 66% and 34%, respectively.

Table IV. Hardware Utilization For Fixed Window Length And 8-bit Word Length On ASIC

Table V. Hardware Utilization For Fixed Window Length And 16-bit Word Length On ASIC

4- Hardware sharing for high system clock and low data throughputs
The memory elements of our architecture cannot be shared and based on the results of the proposed architecture approximately 32% of total area belongs to non-combinational elements. In the proposed architecture, two comparators and a controller in each cell are combinational resources. These elements can be shared. To do so, we can make use of one comparator (instead of two) in each cell; but in this case, we need two clock cycles to generate the output. By this way, in the first clock, the oldest element in the register chain is compared to thecontent of Ri of all array cells in parallel using a comparator in each cell. The old cell in the array cells is specified and the right side elements of this cell i are shifted to the left. In the second clock, the new input sample is compared with the content of all array cells inparallel and the right position for the new sample is located. This position and its right-side elements are shifted right and the new sample is located in this place. Therefore, we can save the area utilization by sharing the comparators. However, the latency is increased to two clock cycles (decreasing the actual working frequency). We can also share the control unit by using a multiplexer, but since its design is simple, it seems that it cannot save the occupied area significantly. Additionally, by adding some multiplexers and slight modification in the control unit, one can also automatically select one of two proposed designs easily. We leave this extension for future research.